Power Distribution System (PDS)

The edge rates of today’s silicon technology require very robust stackup design which utilize appropriate noise filtering (both power plane and crosstalk reduction). Interconnect Engineering can create stackup designs that employ proper PDS design with the following areas of consideration in mind:

  • Stackup design to minimize noise due to crosstalk, SSO, ground bounce, etc. Crosstalk analysis of signals to reduce noise.

  • Use of buried capacitance (plane to plane spacing) for distributed high frequency decoupling.

  • SIwave simulations of PDS to determine if design is suitable.

  • Capacitor type and value choices to ensure broad spectrum of noise reduction. Low Inductance Chip Capacitors (LICC) or Reverse Geometry (RG) capacitors are very useful for decoupling high frequency noise. Tantalum or electrolytic capacitors may be used for low frequency decoupling.

  • Return current analysis for noise reduction (no planes splits).

  • Capacitor type and value chosen to ensure broad spectrum of noise reduction. Capacitor placement and low inductance connections to planes. Place capacitors closest to planes they are meant to decouple (primary or secondary) to further reduce via inductance.

  • Power plane and routing (breakout) study to determine layer count requirements for each design.

  • Simultaneous switching output analysis.

  • Simulations of device I/O to reduce overshoot and undershoot (which can cause increased noise on power planes due to return currents).

  • Crosstalk analysis of signals to reduce noise.

  • Proper transmission line impedance control.

  • Lab measurements using oscilloscopes, spectrum analyzers, etc. for verification.