Double Data Rate (DDR)

Many of today’s high-speed interfaces are employing double data rate, clocking forwarding design. While this has the ability to save on I/O pin/ball count, etc., it can dramatically increase the complexity of the ASIC/FPGA controller and the interface to the board/destination interface environment. Interconnect Engineering can help with these sorts of designs from the design of the controller to the physical layout of the PCB.

  • Familiar with DDR/QDR interfaces (chip-to-chip, SDRAM (SDR/DDR), FCRAM, RLDRAM, CIO/SIO SRAM. Also very familiar with SSTL and HSTL I/O technology and related termination methodology.

  • Simulation of strobe versus data and control with analysis of delay components that can cause interface failure such as:

    • On chip clock skew (FPGA/ASIC).

    • Output buffer skew (data bit to data bit as well as clock).

    • Simultaneous switching delay-adders.

    • Package skew between I/O.

    • Package crosstalk.

    • PCB crosstalk (crosstalk driven delay).

    • Flight time differences between data and control (due to length mismatch, layer differences, via count differences, transmission line effects. etc.

    • Jitter.

    • Edge rate degradation (slew rate requirements being met) as related to input thresholds.