All interfaces that do not have wait-state control are timing sensitive. As such these interfaces must be simulated to understand whether timing will be met or not. Signal integrity plays a huge factor in the timing due to transmission line effects. Un-terminated transmission lines, in addition to potentially causing timing failure can cause part failure over time if ESD diodes conduct. Interconnect Engineering can ensure these issues don’t happen by:
- Using very accurate Hspice trace delay results (normalized relative to output test loading for accuracy), timing margins may be verified over process, voltage, and temperature. There is truly no other way to ensure timing will be acceptable for production and subsequent customer installation environments. Lab verification from a timing (and signal integrity) point of view is fundamentally flawed because the process for the chips on the board is typically unknown.
- Both source synchronous and common-clock timing analysis may be accomplished.
- Topology, termination mechanisms, clock trace length (delay), trace impedance and silicon drive strength may be tailored to bring a timing failure into positive margin (setup and hold).
- Failing interfaces may also be remedied if crosstalk is present. Crosstalk driven delay is becoming a very important and overlooked problem with today’s PCB stackup technology due to shrinking line widths and spaces. Crosstalk needs to be accurately modeled and monitored through simulation and lab measurements respectively.